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HD74HC192, HD74HC193
Synchronous Up/Down Decade Counter (Dual Clock Lines) Synchronous Up/Down 4-bit Binary Counter (Dual Clock Lines)
REJ03D0588-0300 Rev.3.00 Jan 31, 2006
Description
The HD74HC192 is a decade counter, and the HD74HC193 is a binary counter. Both counters have two separate clock inputs, an up count input and a down count input. All outputs of the flip-flops are simultaneously triggered on the low to high transition of either clock while the other input is held high. The direction of counting is determined by which input is clocked. These counters may be preset by entering the desired data on the data A, data B, data C, and data D inputs. When the load input is taken low the data is loaded independently of either clock input. This feature allows the counters to be used as divide-by-n counters by modifying the count length with the preset inputs. In addition both counters can also be cleared. This is accomplished by inputting a high on the clear input. All 4 internal stages are set to a low level independently of either count input. Both a borrow and carry output are provided to enable cascading of both up and down counting functions. The borrow output produces a negative going pulse when the counter underflows and the carry outputs a pulse when the counter overflows. The counters can be cascaded by connecting the carry and borrow outputs of one device to the count up and count down inputs, respectively, of the next device.
Features
* * * * * * High Speed Operation: tpd (Clock Up or Count Down to Q) = 21 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 A max Low Quiescent Supply Current: ICC (static) = 4 A max (Ta = 25C) Ordering Information
Part Name Package Type Package Code (Previous Code) Package Abbreviation -- EL (2,000 pcs/reel) Taping Abbreviation (Quantity)
HD74HC192P PRDP0016AE-B DILP-16 pin P (DP-16FV) HD74HC193P HD74HC192FPEL PRSP0016DH-B SOP-16 pin (JEITA) FP (FP-16DAV) HD74HC193FPEL Note: Please consult the sales office for the above package availability.
Rev.3.00, Jan 31, 2006 page 1 of 13
HD74HC192, HD74HC193
Pin Arrangement
Data B 1 Input QB 2 Outputs QA 3 Count Down Inputs Count Up 4 5 QB QA B A
16 VCC 15 Data A Inputs Clear 14 Clear 13 Borrow Outputs
Count Up
Count Borrow Down
Carry Load D C
12 Carry 11 Load 10 Data C 9 Data D Inputs
QC 6 Outputs QD 7 GND 8
QC QD
(Top view)
Rev.3.00, Jan 31, 2006 page 2 of 13
HD74HC192, HD74HC193
Timing Chart
HD74HC192 Illustrated below is the following sequence: 1. 2. 3. 4. Clear outputs to zero. Load (preset) to binary seven. Count up to eight, nine, zero, one and two. Count down to one, zero, borrow, nine, eight and seven.
Clear Load A Data Inputs B C D Count Up Count Down QA QB QC QD Carry Borrow 8 Sequence Illustrated 0 Clear 7 Preset 9 0 1 2 1 0 9 8 7 Count Up Count Down
Rev.3.00, Jan 31, 2006 page 3 of 13
HD74HC192, HD74HC193
Timing Chart
HD74HC193 Illustrated below is the following sequence: 1. 2. 3. 4. Clear outputs to zero. Load (preset) to binary thirteen. Count up to fourteen, fifteen, zero, one and two. Count down to one, zero, borrow, fifteen and thirteen.
Clear Load A Data Inputs B C D Count Up Count Down QA QB Outputs QC QD Carry Borrow 0 13 14 15 0 1 2 1 0 15 14 13 Count Up Clear Preset Count Down
Rev.3.00, Jan 31, 2006 page 4 of 13
HD74HC192, HD74HC193
Logic Diagram
HD74HC192
Count Down Count Up
CK R Q CK S Q
Borrow
Carry
Data A
CK R Q CK S Q
QA
Data B
CK R Q CK S Q
QB
QC
CK R Q CK S Q
Data C
QD
Data D Load Clear
HD74HC193
Count Down Count Up
CK R Q CK S Q
Borrow
Carry
Data A
CK R Q CK S Q
QA
Data B
CK R Q CK S Q
QB
QC
CK R Q CK S Q
Data C
QD
Data D Load Clear
Rev.3.00, Jan 31, 2006 page 5 of 13
HD74HC192, HD74HC193
Absolute Maximum Ratings
Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings -0.5 to 7.0 -0.5 to VCC +0.5 20 25 50 500 -65 to +150 Unit V V mA mA mA mW C
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
Recommended Operating Conditions
Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Note: Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC -40 to 85 0 to 1000 0 to 500 0 to 400 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Unit V V C ns Conditions
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Electrical Characteristics
Item Input voltage Symbol VCC (V) VIH 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 Min 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.18 5.68 -- -- -- -- -- -- -- Ta = 25C Typ Max -- -- -- -- -- -- 2.0 4.5 6.0 -- -- 0.0 0.0 0.0 -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.26 0.26 0.1 4.0 Ta = -40 to+85C Unit Min Max 1.5 3.15 4.2 -- -- -- 1.9 4.4 5.9 4.13 5.63 -- -- -- -- -- -- -- -- -- -- 0.5 1.35 1.8 -- -- -- -- -- 0.1 0.1 0.1 0.33 0.33 1.0 40 V Test Conditions
VIL
V
Output voltage
VOH
V
Vin = VIH or VIL IOH = -20 A
VOL
V
Vin = VIH or VIL
IOH = -4 mA IOH = -5.2 mA IOL = 20 A
Input current Quiescent supply current
Iin ICC
IOL = 4 mA IOL = 5.2 mA A Vin = VCC or GND A Vin = VCC or GND, Iout = 0 A
Rev.3.00, Jan 31, 2006 page 6 of 13
HD74HC192, HD74HC193
Switching Characteristics
(CL = 50 pF, Input tr = tf = 6 ns)
Item Maximum clock frequency Propagation delay time Symbol VCC (V) fmax 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -- Ta = 25C Ta = -40 to +85C Unit Min Typ Max Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 80 16 14 5 5 5 100 20 17 50 10 9 -- -- -- -- -- -- -- -- 14 -- -- 15 -- -- 14 -- -- 15 -- -- 21 -- -- 21 -- -- 17 -- -- 23 -- -- 24 -- -- 8 - -- -3 -- -- 4 -- -- -1 -- -- 5 -- 5 4 20 24 140 28 24 130 26 22 130 26 22 130 26 22 215 43 37 275 55 47 230 46 39 290 58 49 265 53 45 -- -- -- -- -- -- -- -- -- -- -- -- 75 15 13 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 20 17 5 5 5 125 25 21 65 13 11 -- -- -- -- 3 16 19 175 35 30 165 33 28 165 33 28 165 33 28 270 54 46 345 69 59 290 58 49 365 73 62 335 66 56 -- -- -- -- -- -- -- -- -- -- -- -- 95 19 16 10 MHz Test Conditions
tPLH
ns
Count up to Carry
tPHL
tPLH
ns
Count down to Borrow
tPHL
tPLH
ns
Count up or down to Q
tPHL
tPLH
ns
Load to Q
tPHL
tPHL
ns
Clear to Q
Pulse width
tw
ns
Hold time
th
ns
Data to Load
Setup time
tsu
ns
Data to Load
Removal time
trem
ns
Clear to Clock
Output rise/fall time Input capacitance
tTLH, tTHL
ns
Cin
pF
Rev.3.00, Jan 31, 2006 page 7 of 13
HD74HC192, HD74HC193
Test Circuit
VCC VCC Output
Load
Borrow Output Carry Output CL = 50 pF QA to QD CL = 50 pF CL = 50 pF
See Function Table
Input Pulse Generator Zout = 50
Up Down Clear A B C D
Note : 1. CL includes probe and jig capacitance.
Waveforms
* Waveform - 1 (HD74HC192)
tr Count Up
(Measure at tn+1)
tf VCC
50% 50% 50% 50%
tw (H) tPLH
tw (L) tPHL (Measure at tn+2)
90% 50% 10%
0V VOH VOL tPLH (Measure at tn+2)
90% 50% 10%
QA
90% 50% 10%
tTLH
tTHL tPHL (Measure at tn+4)
90% 50% 10%
VOH VOL
QB
tTHL tPHL (Measure at tn+8) QC
90% 50% 10%
tTLH tPLH (Measure at tn+4)
90% 50% 10%
VOH VOL
tTHL tPHL (Measure at tn+10) QD
(Measure before 1 clock of tn+10)
tTLH tPLH (Measure at tn+8)
90% 50% 10%
90% 50% 10%
VOH VOL
tPHL
tTHL tPLH (Measure at tn+10)
50% 10% 90% 50%
tTLH VOH VOL
90%
Carry
tTHL
tTLH
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. tn is reference bit time when all outputs are low.
Rev.3.00, Jan 31, 2006 page 8 of 13
HD74HC192, HD74HC193
* Waveform - 2 (HD74HC192)
tr Count Down tf VCC
50% 50% 50% 50%
tw (H)
tw (L)
0V tPLH (Measure at tn+0)
50%
tPHL (Measure at tn+1) VOH
50%
QA
VOL tPLH (Measure at tn+2) tPHL (Measure at tn+4) VOH QB
50% 50%
VOL tPLH (Measure at tn+2) tPHL (Measure at tn+6) VOH QC
50% 50%
VOL tPLH (Measure at tn+0) tPHL (Measure at tn+2) VOH QD
(Measure before 1 clock of tn+0)
50%
50%
VOL tPHL tPLH (Measure at tn+0)
90% 50% 10%
Borrow
90% 50%
VOH VOL
tTHL
tTLH
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. tn is reference bit time when outputs are H, L, L, H
Rev.3.00, Jan 31, 2006 page 9 of 13
HD74HC192, HD74HC193
* Waveform - 3 (HD74HC193)
tr Count Up
(Measure at tn+1)
tf VCC
50% 50% 50% 50%
tw (H) tPLH
tw (L) tPHL (Measure at tn+2)
90% 50% 10%
0V VOH VOL tPLH (Measure at tn+2)
90% 50% 10%
QA
90% 50% 10%
tTLH
tTHL tPHL (Measure at tn+4)
90% 50% 10%
VOH VOL
QB
tTHL tPHL (Measure at tn+8) QC
90% 50% 10%
tTLH tPLH (Measure at tn+4)
90% 50% 10%
VOH VOL
tTHL tPHL (Measure at tn+16) QD
(Measure before 1 clock of tn+16)
tTLH tPLH (Measure at tn+8)
90% 50% 10%
90% 50% 10%
VOH VOL
tPHL
tTHL tPLH (Measure at tn+16)
50% 10% 90% 50%
tTLH VOH VOL
90%
Carry
tTHL
tTLH
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. tn is reference bit time when all outputs are low.
Rev.3.00, Jan 31, 2006 page 10 of 13
HD74HC192, HD74HC193
* Waveform - 4 (HD74HC193)
tr Count Down tf VCC
50% 50% 50% 50%
tw (H)
tw (L)
0V tPLH (Measure at tn+0)
50%
tPHL (Measure at tn+1) VOH
50%
QA
VOL tPLH (Measure at tn+0) tPHL (Measure at tn+2) VOH QB
50% 50%
VOL tPLH (Measure at tn+0) tPHL (Measure at tn+4) VOH QC
50% 50%
VOL tPLH (Measure at tn+0) tPHL (Measure at tn+8) VOH QD
(Measure before 1 clock of tn+0)
50%
50%
VOL tPHL tPLH (Measure at tn+0)
90% 50% 10%
Borrow
90% 50%
VOH VOL
tTHL
tTLH
Notes : 1. Input pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. tn is reference bit time when outputs are H, L, L, H
Rev.3.00, Jan 31, 2006 page 11 of 13
HD74HC192, HD74HC193
* Waveform - 5
tr
90 % 50 % 50 % 10 %
tf VCC
10 %
Clear
0V tf
90 % 50 % 90 % 50 % 10 %
tW tr Data (A to D) VCC
50 %
10 %
t su tf Load
90 % 50 % 10 %
th
t su
th
0V
90 % 50 % 10 % 50 % 50 %
VCC 0V
t PHL
90 %
t PLH
tr
90 %
t PHL
90 % 50 % 10 %
VOH VOL
Q
50 % 10 %
50 % 10 %
t THL
t TLH
t THL
Notes : 1. Load Input Pulse : PRR 1 MHz, Zo = 50 , tr 6 ns, tf 6 ns 2. Data Input Pulse : PRR 500 kHz, Zo = 50 , tr 6 ns, tf 6 ns
Rev.3.00, Jan 31, 2006 page 12 of 13
HD74HC192, HD74HC193
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.3.00, Jan 31, 2006 page 13 of 13
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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